Reconfigurable Processing Unit Research Articles

RF Frequency Selective Switch by Multiple PMIM Conversions

Nowadays, broadband and multi-channel radio frequency (RF) processing has been widely used in communication, radar, countermeasure, and other applications. At present, multiple-input and multiple-output (MIMO)-oriented microwave photonic signal processing technology is relatively scarce, so this paper proposes an RF frequency selective switch (FSS) based on multiple phase modulation to intensity modulation (PMIM) conversions. PMIM conversion has been used in narrowband microwave photonic filtering in the past. We extend it to a wideband and arbitrarily reconfigurable RF spectrum processing unit through an optical frequency comb and periodic optical filter. Although we use the incoherent combination of a multi-wavelength light source, we can obtain any frequency response including rectangles only by using all positive tap coefficients. Using an optical wavelength selective switch (WSS), we obtain RF FSS, and the spectral resolution of RF FSS is much better than that of optical WSS, which is improved by more than two orders of magnitude. The above principles, including single-channel reconfigurable filtering and multi-channel RF FSS, are verified by experiments. Our technology provides a stable solution for future RF MIMO signal processing.

Design and Implementation of a Coarse-grained Dynamically Reconfigurable Multimedia Accelerator

This article proposes and implements a Coarse-grained dynamically Reconfigurable Architecture, named Reconfigurable Multimedia Accelerator (REMAC). REMAC architecture is driven by the pipelined multi-instruction-multi-data execution model for exploiting multi-level parallelism of the computation-intensive loops in multimedia applications. The novel architecture of REMAC's reconfigurable processing unit (RPU) allows multiple iterations of a kernel loop can execute concurrently in the pipelining fashion by the temporal overlapping of the configuration fetch, execution, and store processes as much as possible. To address the huge bandwidth required by parallel processing units, REMAC architecture is proposed to efficiently exploit the abundant data locality in the kernel loops to decrease data access bandwidth while increase the efficiency of pipelined execution. In addition, a novel architecture of dedicated hierarchy data memory system is proposed to increase data reuse between iterations and make data always available for parallel operation of RPU. The proposed architecture was modeled at RTL using VHDL language. Several benchmark applications were mapped onto REMAC to validate the high-flexibility and high-performance of the architecture and prove that it is appropriate for a wide set of multimedia applications. The experimental results show that REMAC's performance is better than Xilinx Virtex-II, ADRES, REMUS-II, and TI C64+ DSP.

High-Performance Reconfigurable Architecture for Lightweight Block Ciphers

Aiming at the problem that the current hardware implementation architecture using ASIC is difficult to meet the flexibility requirements of different applications, a high-performance reconfigurable architecture for lightweight block cipher (HRALBC) is proposed. By analyzing 42 mainstream lightweight block cipher algorithms, the pattern features and combination features of the algorithm are extracted; The reconfigurable processing unit is designed based on the pattern feature results and combined feature results; The reconfigurable processing unit array is designed according to the algorithm mapping law, and then the overall architecture is designed. Map different types of algorithms to HRALBC, verify their functional correctness, and analyze the mapping results. The experimental results show that under TSMC 55 nm CMOS process, the working frequency of HRALBC can reach 429 MHz, and the total area is 1.23M equivalent gate (GE). For different cryptographic algorithms, the area efficiency can be up to 22.33 Gbit·s^-1·MGE^-1. Compared with the Anole, for PRESENT64/80, SPECK64/128 and SIMON64/128 algorithms, the utilization of reconfigurable units is increased by 16.67%, 16.67% and 13.89% respectively, and the area efficiency is increased by 66.64%, 66.64% and 11.04% respectively.

Acceleration of Rotated Object Detection on FPGA

In this brief, an FPGA-based solution is proposed to show the computing efficiency on rotated object detection based on R <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> Det algorithm. The key idea of our approach is firstly to design reconfigurable neural processing units (NPU) for convolutional neural networks (CNN) and a specific architecture for spatial operations, and then to adopt a novel scheduling scheme to deal with the data dependency on these modules. When implemented on cost-effective Kintex Ultrascale+ XCKU15P FPGA, the proposed solution achieves nearly 3.20 times energy efficiency compared to NVIDIA V100 GPU. The proposed reconfigurable NPU achieves 73.20% DSP efficiency, 30.39% improvement compared to the 56.14% DSP efficiency of the state-of-the-art CNN accelerator on ResNet-50.

A 67.5μJ/Prediction Accelerator for Spiking Neural Networks in Image Segmentation

Spiking Neural Networks (SNNs) is promising to enable low power and high performance edge computing hardware design and have recently attracted attentions of researchers. Compared to Artificial Neural Networks (ANNs), SNNs, which present more realistic brain-inspired computing models, are developed as an alternative to ANNs. However, the temporal primitive of SNNs causes irregular and repeated data accesses, leading to high latency and extra power consumption. In this work, we propose an efficient architecture for SNNs by exploiting event-based characteristics. A reconfigurable spiking neuron processing unit is proposed to support a variety of spike-layers. Furthermore, to reduce the cycles needed per frame, an efficient dataflow with fast-filtering mechanism is introduced to leverage the sparsity of discrete spikes. The results show that this design achieves 67.5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{J}$ </tex-math></inline-formula> /image prediction energy with a throughput of 2.2K FPS. The core size is 0.89 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> under 28-nm technology, with 90.98% computing hardware utilization and a competitive accuracy 97.10% on a driving dataset.

Breaking TrustZone memory isolation and secure boot through malicious hardware on a modern FPGA-SoC

FPGA-SoCs are heterogeneous embedded computing platforms consisting of reconfigurable hardware and high-performance processing units. This combination offers flexibility and good performance for the design of embedded systems. However, allowing the sharing of resources between an FPGA and an embedded CPU enables possible attacks from one system on the other. This work demonstrates that a malicious hardware block contained inside the reconfigurable logic can manipulate the memory and peripherals of the CPU. Previous works have already considered direct memory access attacks from malicious logic on platforms containing no memory isolation mechanism. In this work, such attacks are investigated on a modern platform which contains state-of-the-art memory and peripherals isolation mechanisms. We demonstrate two attacks capable of compromising a Trusted Execution Environment based on ARM TrustZone and show a new attack capable of bypassing the secure boot configuration set by a device owner via the manipulation of Battery-Backed RAM and eFuses from malicious logic.

Large-scale neuromorphic optoelectronic computing with a reconfigurable diffractive processing unit

Application-specific optical processors have been considered disruptive technologies for modern computing that can fundamentally accelerate the development of artificial intelligence (AI) by offering substantially improved computing performance. Recent advancements in optical neural network architectures for neural information processing have been applied to perform various machine learning tasks. However, the existing architectures have limited complexity and performance; and each of them requires its own dedicated design that cannot be reconfigured to switch between different neural network models for different applications after deployment. Here, we propose an optoelectronic reconfigurable computing paradigm by constructing a diffractive processing unit (DPU) that can efficiently support different neural networks and achieve a high model complexity with millions of neurons. It allocates almost all of its computational operations optically and achieves extremely high speed of data modulation and large-scale network parameter updating by dynamically programming optical modulators and photodetectors. We demonstrated the reconfiguration of the DPU to implement various diffractive feedforward and recurrent neural networks and developed a novel adaptive training approach to circumvent the system imperfections. We applied the trained networks for high-speed classifying of handwritten digit images and human action videos over benchmark datasets, and the experimental results revealed a comparable classification accuracy to the electronic computing approaches. Furthermore, our prototype system built with off-the-shelf optoelectronic components surpasses the performance of state-of-the-art graphics processing units (GPUs) by several times on computing speed and more than an order of magnitude on system energy efficiency.

Efficient scheduling mapping algorithm for row parallel coarse-grained reconfigurable architecture

Row Parallel Coarse-Grained Reconfigurable Architecture (RPCGRA) has the advantages of maximum parallelism and programmable flexibility. Designing an efficient algorithm to map the diverse applications onto RPCGRA is difficult due to a number of RPCGRA hardware constraints. To solve this problem, the nodes of the data flow graph must be partitioned and scheduled onto the RPCGRA. In this paper, we present a Depth-First Greedy Mapping (DFGM) algorithm that simultaneously considers the communication costs and the use times of the Reconfigurable Cell Array (RCA). Compared with level breadth mapping, the performance of DFGM is better. The percentage of maximum improvement in the use times of RCA is 33% and the percentage of maximum improvement in non-original input and output times is 64.4% (Given Discrete Cosine Transfor 8 (DCT8), and the area of reconfigurable processing unit is 56). Compared with level-based depth mapping, DFGM also obtains the lowest averages of use times of RCA, non-original input and output times, and the reconfigurable time.

Performance-driven parallel reconfigurable computing architecture for multi-standard video decoding

Video processing applications often need high computing capacity but have performance and power constraints, especially in portable devices. General purpose processors can no longer meet the requirements. This paper presents a parallel reconfigurable computing architecture consisting of reconfigurable processing units connected by an area-efficient routing. The hierarchical configuration contexts can cut the implementation overhead and the energy dissipation spent on fast reconfiguration. The proposed architecture targets multiple-standard video processing. The design is able to give high performance comparable to the fixed-function ASIC through deep pipelining and a large amount of computing parallelism. The experimental results show the proposed architecture has great performance and practicability.

Reconfigurable Architecture for Multi-lead ECG Signal Compression with High-frequency Noise Reduction

Electrocardiogram (ECG) is a record of the heart’s electrical activity over a specified period, and it is the most popular noninvasive diagnostic test to identify several cardiac diseases. It is an integral part of a typical eHealth system, where the ECG signals are often needed to be compressed for long term data recording and remote transmission. Reconfigurable architecture offers high-speed parallel computation unit, particularly the Field Programmable Gate Array (FPGA) along with adaptable software features. Hence, this type of design is suitable for multi-channel signal processing units like ECGs, which usually require precise real-time computation. This paper presents a reconfigurable signal processing unit which is implemented in ZedBoard- a development board for Xilinx Zynq −7000 SoC. The compression algorithm is based on Fast Fourier Transformation. The implemented system can work in real-time and achieve a maximum 90% compression rate without any significant signal distortion (i.e., less than 9% normalized percentage of root-mean-square deviation). This compression rate is 5% higher than the state-of-the-art hardware implementation. Additionally, this algorithm has an inherent capability of high-frequency noise reduction, which makes it unique in this field. The confirmatory analysis is done using six databases from the PhysioNet databank to compare and validate the effectiveness of the proposed system.

Implementation of in‐loop filter for HEVC decoder on reconfigurable processor

The in-loop filter comprises deblocking filter and sample adaptive offset filter, which is an important module for improving image quality in a high-efficiency video coding (HEVC) decoder. The in-loop filter has a high computational complexity that accounts for ∼20% of the HEVC decoding computing load. Furthermore, it is difficult to implement a high-performing in-loop filter due to its large conditional processing requirement. First, this study presents a novel reconfigurable HEVC in-loop filter implementation on a coarse-grained dynamically reconfigurable processing unit. Next, a repartition scheme is presented that allows the in-loop filter implementation at a coding tree unit along with the other decoding modules in the HEVC decoder, which satisfies requirements of low latency applications. Finally, a hierarchised-pipeline and synchronised-parallel technique is used to improve performance by eliminating data hazards in pipeline techniques and synchronisation problems in parallel techniques. Implementation results show that the presented HEVC in-loop filter performs up to 1920 × 1080@52 frames per second at 250 MHz. The throughput is 67.5 × 9 × more than solutions based on digital signal processor and general-purpose processor, respectively.

Design and Implementation of Configurable SHIFT Instructions Targeted at Symmetrical Cipher Processing

High-performance and flexible configurable SHIFT instructions targeted at symmetrical cipher processing are proposed in this paper, in order to dispel the bottleneck of symmetrical cipher algorithms realized by universal processors. Through analyzing the processing characteristics and the structures of many symmetrical cipher algorithms, the proposed SHIFT instructions can support different processing data widths, different SHIFT modes. Furthermore, instruction level parallelism based on VLIW system structure and instruction inner parallelism by operating several sub word SHIFTs at the same time are designed too. Finally, corresponding reconfigurable hardware units to support the execution of each instruction forcefully is also exploited. For the characteristics of high efficiency and flexibility, the specific SHIFT instructions and the reconfigurable hardware processing units can be used as an ameliorative unit for processors to advance the performance in special processing for symmetrical cipher.

Pulse-signal digitizer for high-temperature plasma diagnostic systems

A pulse-signal digitizer for laser, neutron, and gamma diagnostics of high-temperature plasma at the GOL-3 and GDL (Budker Institute of Nuclear Physics Siberian Branch, Russian Academy of Sciences) is described. The architecture of a two-channel 12-bit ADC12500PXIe digitizer with a sampling rate of 500MHz, a PXI Express interface, and a built-in reconfigurable digital signal processing unit is described. The results of ADC12500PXIe metrological tests are presented: its signal-to-noise ratio (SNR), jitter, effective number of bits, and differential and integral nonlinearities are shown. The high-temperature plasma diagnostic systems based on ADC12500PXIe are considered. The structure of the digital signal processing unit that was modified for a prototype of the ITER vertical neutron camera (Cadarache, France) is described.

An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding

A coarse-grained reconfigurable processing unit (RPU) consisting of 16 ×16 multi-functional processing elements (PEs) interconnected by an area-efficient line-switched mesh connect (LSMC) routing is implemented on a 5.4 mm ×3.1 mm die in TSMC 65 nm LP1P8M CMOS technology. A hierarchical configuration context (HCC) organization scheme is proposed to reduce the implementation overhead and the energy dissipation spent on fast reconfiguration. The proposed RPU is integrated into two system-on-a-chips (SoCs), targeting multiple-standard video decoding. The high-performance chip, comprising two RPU processors (named REMUS_HPP), can decode 1920 ×1080 H.264 video streams at 30 frames per second (fps) under 200 MHz. REMUS_HPP achieves a 25% performance gain over the XPP-III reconfigurable processor with only 280 mW power consumption, resulting in a 14.3 × improvement on energy efficiency. The other chip (named REMUS_LPP), targeting low power applications, integrates only one RPU processor. REMUS_LPP can decode 720 ×480 H.264 video streams at 35fps with 24.5 mW under 75 MHz, achieving a 76% reduction in power dissipation and a 3.96 × improvement on energy efficiency compared with the ADRES reconfigurable processor.

A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses

This article presents a reconfigurable hardware/software architecture for binary acceleration of embedded applications. A Reconfigurable Processing Unit (RPU) is used as a coprocessor of the General Purpose Processor (GPP) to accelerate the execution of repetitive instruction sequences called Megablocks . A toolchain detects Megablocks from instruction traces and generates customized RPU implementations. The implementation of Megablocks with memory accesses uses a memory-sharing mechanism to support concurrent accesses to the entire address space of the GPP’s data memory. The scheduling of load/store operations and memory access handling have been optimized to minimize the latency introduced by memory accesses. The system is able to dynamically switch the execution between the GPP and the RPU when executing the original binaries of the input application. Our proof-of-concept prototype achieved geometric mean speedups of 1.60× and 1.18× for, respectively, a set of 37 benchmarks and a subset considering the 9 most complex benchmarks. With respect to a previous version of our approach, we achieved geometric mean speedup improvements from 1.22 to 1.53 for the 10 benchmarks previously used.

SimRPU: A Simulation Environment for Reconfigurable Architecture Exploration

To assist the system architects with fast exploration and performance evaluation of the reconfigurable software/hardware architectures, this paper presents a system-level simulator, named after SimRPU, for the reconfigurable processing unit (RPU), which is the major computing engine in reconfigurable processor. The proposed simulator consists of a simulation kernel, a software compiler, a system profiler providing performance, area and power information for the desired architectures, and a system debugger supporting inspecting and modification of the internal state of the RPU. Object-oriented hierarchical and parameterized architecture modeling techniques are proposed to satisfy the requirements for a fast and comprehensive evaluation. Cycle-accurate simulation mechanisms are developed to improve the accuracy of the profiled performance data. Compared with the traditional register transfer level (RTL) based simulation scheme, the proposed simulator could achieve an average speedup of 18.5× with only 3.5% reduction on performance estimation accuracy. One reconfigurable processor targeted at high-definition multimedia decoding applications (such as H.264, MPEG2, AVS, etc.) is implemented with Taiwan Semiconductor Manufacturing Company 65-nm process using the proposed exploration and design flow. The measured results show that the implemented architecture has obvious advantages in terms of both performance and power consumption than the reference designs in multimedia decoding applications.

Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system

In this paper, a TPP (Task-based Parallelization and Pipelining) scheme is proposed to implement AVS (Audio Video coding Standard) video decoding algorithm on REMUS (REconfigurable MUltimedia System), which is a coarse-grained reconfigurable multimedia system. An AVS decoder has been implemented with the consideration of HW/SW optimized partitioning. Several parallel techniques, such as MB (Macro-Block)-based parallel and block-based parallel techniques, and several pipeline techniques, such as MB level pipeline and block level pipeline techniques are adopted by hardware implementation, for performance improvement of the AVS decoder. Also, most computation-intensive tasks in AVS video standards, such as MC (Motion Compensation), IP (Intra Prediction), IDCT (Inverse Discrete Cosine Transform), REC (REConstruct) and DF (Deblocking Filter), are performed in the two RPUs (Reconfigurable Processing Units), which are the major computing engines of REMUS. Owing to the proposed scheme, the decoder introduced here can support AVS JP (Jizhun Profile) 1920×1088@39fps streams when exploiting a 200 MHz working frequency.

Implementation of multi-standard video decoder on a heterogeneous coarse-grained reconfigurable processor

This paper proposes a task-based hybrid parallel and hybrid pipeline (THPHP) scheme to implement multi-standard video algorithms, including MPEG-2, H.264, and audio video coding standard (AVS), on a heterogeneous coarse-grained reconfigurable processor, called the reconfigurable multimedia system (REMUS). The proposed schemes greatly improve decoding performance and satisfy the real-time requirements of various high-definition (HD) video decoding standards. In THPHP, we propose both a task-based hybrid parallel scheme, in which macro-block (MB)-level, block-level, and sub-block-level decoding tasks are parallelized to improve data processing throughput, and a hybrid pipeline scheme, in which slice-level, MB-level, block-level and sub-block-level computations are pipelined to improve efficiency. Computation-intensive tasks, such as motion compensation, intra prediction, inverse discrete cosine transform, reconstruction, and deblocking filter, are implemented on two reconfigurable processing units, which are the core computing engines of REMUS. Thanks to the proposed schemes, the implementations can achieve H.264 high profile (HP) 1920×1080@30 fps streams, AVS Jizhun profile (JP) 1920×1080@39 fps streams, and MPEG-2 main profile (MP) 1920×1080@41 fps streams when working at 200 MHz frequency. Compared with XPP-III (a commercial reconfigurable processor), when implementing H.264 HD decoding, the performance and energy efficiency on REMUS are improved by 1.81× and 14.3×, respectively.

On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time

The coarse-grained reconfigurable architecture (CGRA) is proven to be energy efficient in several specific domains. In CGRAs, the on-chip memory hierarchy, which contains the context memory and the data memory organizations, should be well considered to achieve appropriate tradeoffs among three aspects: 1) performance; 2) area; and 3) power. In this paper, two techniques called the hierarchical configuration context (HCC) and the lifetime-based data-memory organization (LDO) focusing on the context memory and the data memory organizations are proposed to compress the on-chip memory space and to reduce the reconfiguration time and the data-reference time. In the HCC, the contexts are constructed in a hierarchical fashion to completely eliminate the repetitive portions of the contexts, not only reducing the overall context storage, but also alleviating the context transportation overhead. A fast context-indexing mechanism in the HCC is proposed to achieve fast reconfiguration, as the hierarchically organized contexts can be located and accessed conveniently. In the LDO, the on-chip data are classified into two types, based on the lifetime of data. The short-lifetime data are stored in the first in first out to increase the reuse ratio of memory space automatically, whereas the long-lifetime data are stored in the radom access memory for several time references. The HCC and the LDO are used in a CGRA core called as reconfigurable processing unit (RPU). Two RPUs are integrated in a reconfigurable computing processor (RCP) called as REconfigurable MUlti-media System, High-Performance Processor (REMUS_HPP). Because of the HCC, compared with a traditional nonhierarchical system, the total context storage required in H.264 decoding is reduced by 77%. Because of the LDO, the normalized on-chip data memory size at same performance level in the REMUS_HPP is only 23.8% and 14.8% of those in XPP-III (a high-performance RCP) and ADRES (a low-power RCP). REMUS_HPP is implemented on a 48.9-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> silicon with TSMC 65-nm technology, using a 200-MHz working frequency to achieve 1920 × 1088 at 30 fps H.264 high-profile decoding. Compared with XPP-III, the performance of the REMUS_HPP is 1.81× boosted, whereas the energy efficiency is 4.75× higher.

A reconfigurable processor architecture combining multi-core and reconfigurable processing units

It's a promising way to improve performance significantly by adding reconfigurable processing unit (RPU) to a general purpose processor. In this paper, a Reconfigurable Multi-Core (RMC) architecture combining general multi-core and reconfigurable logic is proposed. Reconfigurable logic is separated into RPUs logically, which are coupled with general purpose cores as co-processors via a full crossbar switch. An RPU Manager (RPU-M) is also designed to manage RPUs. To verify RMC, a simulation method based on the Simics and Virtex 5 FPGA is adopted, which simplifies the simulation and assures the evaluation accuracy of hardware function cores. Five workloads are selected to test RMC, including 3-DES, AES, SHA2, IDCT and JPEG_ENC. The experimental results show a 3.10 times average speedup over software implementation on the original multi-core, and the data and control communication overhead on RMC is acceptable.